IEEE

Hardware Trojan Detection using Unsupervised Machine Learning Algorithms in the Gate-level Netlist

Abstract: Now-a-days, the density of gates in VLSI circuits is rapidly increasing, it is becoming more difficult to detect malicious circuits. The malicious nets present in the circuit, named ...
IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...