EDN

Updated Verilog – 2001 Tutorial

The following tutorial, by Stuart Sutherland of Sutherland HDL, is an updated version of a paper presented at HDLCon in March 2000. It provides an overview of the changes in the Verilog-2001 standard.
Design-Reuse

nSys Announces the Release of AS nVS, a Verification Solution for Advanced Switching in Verilog

INTEL DEVELOPER FORUM, San Francisco, CA, September 9, 2004 – nSys (Netsys Software Pvt. Ltd.), a rapidly emerging provider of Verification IPs for emerging standards today announced nVS for the ...
Hackaday

6502 Goes FPGA (Again)

While there has been no shortage of FPGA-based recreations of classic processors, we always enjoy seeing a new approach. Last month [Some Assembly Required] took on the challenge to recreate a classic ...