EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Design-Reuse

MindTree develops 'e' to SystemVerilog language migration utility

July 28, 2009 -- SystemVerilog (SV) along with its methodologies is emerging as a unified language for design and verification using object oriented techniques. Companies who have already invested in ...
Design-Reuse

Borrowing from software to use SystemVerilog test bench debug & analysis

Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

THE SYSTEMVERILOG INFRASTRUCTURE is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
EDN

Book describes writing testbenches using SystemVerilog

SAN FRANCISCO — A book about writing testbenches using SystemVerilog, written by Synopsys Inc.'s Janick Bergeron, has been published by Springer Science + Business Media, the company announced.
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.