System-level test (SLT), once used largely as a stopgap measure to catch issues missed by automated test equipment (ATE), has evolved into a necessary test insertion for high-performance processors, ...

Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for ...

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...

As artificial intelligence fuels rapid growth in high-performance computing, it's also triggering a shift in how semiconductor chips are tested. Beyond leading AI GPU makers, major cloud ...