EDN

VHDL simulator flags inadequately tested code

The CoValidator VHDL simulator and coverage analyzer, the first component of Impulse's forthcoming CoDeveloper hardware/software design suite, enables users to quickly identify specific lines of code ...
Hackaday

Simulating VHDL Of An AVR8 Soft Processor

Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8-bit ...
Electronic Design

Simulation Tools Speed Design Debug And Verification

Shorter time-to-market cycles and the increasing densities of both programmable logic devices (PLDs) and system-on-a-chip (SoC) ICs have made design simulation an essential part of the development ...
mccormick.northwestern.edu

COMP_ENG 355: ASIC and FPGA Design

This course will introduce students to practical design methodologies for developing applications for FPGAs and ASICs. You will learn the fundamentals for FPGA and ASIC design through software coding ...
EDN

Ansoft approves VHDL-AMS models for use with simulator

Ansoft reports that it has certified the VHDL-AMS models from the FAT-AK30 working group of the German Association of the Automotive Industry (Verband der Automobilindustrie, VDA) to run in Simplorer, ...
TechRepublic

Implementation of Digital QPSK Modulator by Using VHDL/MATLAB

The modulators are the basic requirement of the communication systems they are designed to reduce the channel distortion & to use in RF communication hence many type of carrier modulation techniques ...
Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...