The growing demand for cheap consumer wireless applications calls for unprecedented levels of integration. Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, ...

The introduction of high-density ASICs and multimillion-gate FPGAs has brought with it a new class of signal integrity problems, both on-chip and off. On-chip parasitic extraction and interconnect ...

In today’s ever-shrinking IC package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle.

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

Yesterday, I started to talk about how new technologies find their way over time into EDA tools in my post How Technologies Get into EDA. Let’s look at signal integrity as an example. We used not to ...

Analyzing high speed datacom interfaces is an important task and ensures signal integrity. One major challenge of this analysis is the connection between the physical interface and the oscilloscope, ...

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...

Signal integrity (SI) and power integrity (PI) are two distinct but related realms of analysis concerned with proper operation of digital circuits. In signal integrity, the main concern is making sure ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...