EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
EDN

What’s required for golden RTL?

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...
Electronic Design

A Good Methodology Helps Design Teams Check RTL Code

Many of today's large, complex designs can contain thousands of lines of Verilog or VHDL code. Quite often, teams of engineers—with some members possibly situated in disparate locations worldwide—will ...
Design-Reuse

HD Lab, Inc. Releases "SystemC Behavioral Synthesis Style Guide"

Shin-Yokohama, Japan – July 23, 2007-- HD Lab, Inc., announced today the availability of its "SystemC Behavioral Synthesis Style Guide†, a reference book that documents production-proven expertise ...