Fix as many design issues as possible in the RTL code while ensuring that the implementation flow does not introduce new ...

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...

Axis Systems has developed an emulation and verification tool specifically aimed at users of intellectual property. RCC Model Compiler can link together pre-compiled blocks of RTL code. This allows ...

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool ...

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...

LOS GATOS, Calif./SAN JOSE, Calif. - October 8, 2001 - Adaptive Silicon, Inc. (ASi) of Los Gatos, Calif., and Atrenta Inc. of San Jose, Calif., today announced that ASi is developing an Adaptive ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, ...

AI chip design startup ChipAgents has raised $21 million in an oversubscribed Series A funding round. The fundraising saw ...