EDN

Microsemi’s Libero SoC v11.7 Software Increases Security, Usability and Efficiency for FPGA Designs, Enabling Faster Time-to-Market

“The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ...
EDN

Design software for SoC FPGAs speeds run-times

Libero SoC v11.4, Microsemi says, makes significant FPGA design productivity gains with runtime improvements of up to 35%. Productivity enhancements are enabled by improved SERDES design wizards, I/O ...
Business Insider

Microsemi Announces Libero SoC v11.8 Software Providing FPGA Designers Mixed Language Simulation and Best-in-Class Debugging Capabilities

ALISO VIEJO, Calif., April 11, 2017 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, ...
Design-Reuse

Actel Strengthens Libero Integrated Design Environment for Next-Generation FPGA Designs

SUNNYVALE, Calif., February 12, 2003 - Actel Corporation (Nasdaq: ACTL), a supplier of innovative programmable logic solutions, today announced it has enhanced its Actel Liberoâ„¢ integrated design ...
Design-Reuse

Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor

Company's Libero IDE Also Bolsters Industry-Leading Static Timing Analysis and I/O Capabilities MOUNTAIN VIEW, Calif., Nov 02, 2005-- Actel Corporation (Nasdaq: ACTL) today unveiled significant new ...
New Electronics

Libero SoC v11.8 software provides debugging capabilities

The latest version of Microsemi’s Libero SoC software – version 11.8, a comprehensive suite of FPGA design tools – has been released. In addition to the software release, which includes enhancements ...
Electronic Design

RISC-V FPGA Design Leaps Forward with Mi-V

A longtime supporter of the RISC-V (pronounced RISC Five) instruction set architecture (ISA), Microsemi provides tools and RISC-V soft cores for its various FPGA lines, including the recently unveiled ...
Electronic Design

Libero SoC v11.4 Software Improves FPGA Runtime Up To 35%

According to Microsemi, its updated Libero System-On-Chip (SoC) version 11.4 software reduces design flow runtime by up to 35% and timing analysis runtime by 20% for the company’s SmartFusion and ...
Electronics Weekly

FPGA’s fast track to power efficient edge AI

For developers unfamiliar with FPGAs, conventional FPGA development methods can seem complex, often causing developers to turn to less optimal solutions, says Rolf Horn at Digi-Key Electronics.
New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...