EDN

A second look at jitter: Calculating bit error rates

A previous article on jitter (Synch and clock recovery – an analog guru looks at jitter) defined jitter and its various sub-components. The purpose of this note is to answer the question, “So now that ...
Electronic Design

Bit-Error-Rate Testers Face Ethernet Speed Challenges

This file type includes high resolution graphics and schematics when applicable. The bit error ratio (BER) is defined as the probability that a bit is received in ...
EDN

Modulation roundup: error rates, noise, and capacity

Subscribe here to receive similar articles over e-mail whenever Krishna Pillai publishes an article on his site. The article compares various digital modulation schemes like BPSK, QPSK, PAM, 16PSK, ...
Electronic Design

Low-Density Parity Check Error Correction for Solid State Storage

Error Correcting Code (ECC) technology, such as Low-Density Parity Check codes, has been around longer than most of you reading this have been alive. The reason is ...
Semiconductor Engineering

HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes

Hybrid Active-Reactive Profiling (HARP), a new error profiling algorithm that rapidly achieves full coverage of at-risk bits in memory chips that use on-die ECC ...