Ars Technica

ASIC design/verification or embedded systems programming

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...
Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

Verification Platform Speeds Simulation And Emulation

R>epresenting a multifunction verification platform that provides both simulation acceleration and in-circuit emulation capabilities, the Palladium ASIC design ...
Semiconductor Engineering

Synopsys FPGA Platform: Enabling Faster Design, Verification and Debug of FPGAs

FPGA development teams are adopting ASIC-style design, verification and debug methodologies. Here are the necessary elements of such a flow. September 11th, 2019 - By: Synopsys Field programmable gate ...
EDN

Synplicity unveils at-speed ASIC verification

Synplicity has released its Confirma platform, a tightly-integrated, hardware-assisted verification platform for ASIC and ASSP designs. Confirma targets FPGA-based prototyping of designs with three ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Electronic Design

Mixed-signal ASIC Design Meets Tight Deadline

Emerson, AMIS complete mixed-signal project in less than 50 weeks, half the time generally needed to complete such a project Orders were up for Emerson Process Management’s largest-selling product ...
Design-Reuse

eInfochips Offers SystemVerilog Migration Services from Legacy Verification Environments

Ahmedabad, India and Santa Clara, CA - January 20, 2005-- eInfochips, Inc., a leading silicon and product design services firm with spec-to-silicon-to-system capabilities, today announced the ...
Design-Reuse

eASIC announces NEW ASIC-in-a-box Design Kits

Santa Clara, CA − September 29, 2009 − eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of two ASIC-in-a-Box design kits that enable ASIC design to be ...